1. Technical Field
Various embodiments may generally relate to a semiconductor integrated circuit device, and more particularly, to an impedance calibration circuit and a semiconductor memory device including the same.
2. Related Art
A semiconductor memory device consists of a receiver circuit configured to receive a signal from an external device, and a transmitter circuit configured to transmit a signal within the semiconductor memory device.
The signals of the receiver circuit and the transmitter circuit in the semiconductor memory device have a swing width related to a speed of the semiconductor memory device. As the speed of the semiconductor memory device increases, the swing width decreases to minimize a delay time for transmitting the signal.
When the swing width of the signal is decreased, influences caused by external noises increase. Further, an impedance mismatch may be generated at an impedance terminal of the semiconductor memory device.
The impedance mismatch is caused by the external noises, variations of a power voltage, variations of an operational voltage, variations of a fabrication process, etc.
Therefore, in order to ensure a rapid transmission of data and to output reliable data, it may be required to perform an impedance match.
The semiconductor memory device may be operated by a plurality of operational voltages. It may be required to perform the impedance match with levels of the operational voltages.